1. Field of the Invention
This invention relates to semiconductor devices and wire bonding chip size packages (WBCSP) therefor.
This application claims priority on Japanese Patent Application No. 2004-256860, the content of which is incorporated herein by reference.
2. Description of the Related Art
Recently, great technological advances have been achieved with respect to electronic devices such as notebook personal computers and portable telephones (or cellular phones) having digital cameras, thus realizing reduction of dimensions, reduction of thickness, and reduction of weight. For this reason, conventionally known dual inline packages have been replaced with chip size packages incorporating semiconductor devices (or semiconductor elements).
As a typical example of a chip size semiconductor device, Japanese Unexamined Patent Publication No. 2000-68405 discloses a chip size package (CSP) in which a semiconductor element is connected to a carrier substrate via metal bumps, which are formed on the lower surface of the carrier substrate so as to realize packaging with a printed-wiring board.
FIG. 10 is a cross-sectional view showing a conventionally known cross-sectional structure of a chip size package. That is, a chip size package 1 of FIG. 10 is designed such that a plurality of electrode pads 3 are formed in a prescribed pattern on an upper surface 2a of a semiconductor chip 2, onto which a base substrate 5 having the substantially same size as the semiconductor chip 2 is adhered and fixed via an adhesive layer 4, wherein signal wires 6, power wires 7, and ground wires 8 are arranged on an upper surface 5a of the base substrate 5 and are respectively accompanied by lands 6a, 7a, and 8a, which are further accompanied by ball bumps 9 serving as external terminals (which are used to establish connections with external devices). Through holes 10 running vertically through the base substrate 5 are formed at prescribed positions corresponding to the electrode pads 3. The electrode pads 3 and the wires 6 to 8 are respectively connected together via bonding wires 11. Furthermore, the upper surface 5a of the base substrate 5 is covered with a protection film 12 having insulating ability except for in prescribed areas corresponding to the ball bumps 9.
Japanese Unexamined Patent Publication No. H11-284020 discloses an example of a wire bonding chip size package (WBCSP) in which metal pads used for establishing direct connections with external devices are formed on the surface of a semiconductor substrate on which electronic circuits are formed.
FIG. 11 is a cross-sectional view showing a conventionally known cross-sectional structure of a wire bonding chip size package. That is, a WBCSP 21 is designed such that two lines of electrodes 23 are arranged in the longitudinal direction on the center area of an upper surface 22a of a semiconductor chip 22, wherein insulating films 24 are formed on both sides of the electrodes 23, and two lines of conduction pads 25 are formed on each of the insulating films 24 in the longitudinal direction of the semiconductor chip 22.
The conduction pads 25 and the electrodes 23 are connected together via bonding wires 26, wherein the bonding wires 26 are appropriately arranged in consideration of the directivity thereof and the points of connection with the conduction pads 25 in such a way that they do not mutually come in contact with each other and will not be short-circuited. Bump electrodes 27 are fixed onto the conduction pads 25. All components such as the electrodes 23, insulating films 24, conduction pads 25, and bonding wires 26 are covered with a protection film 28 having insulating ability except for in prescribed areas including top portions of the bump electrodes 27, which partially project above the overall upper surface.
In the CSP 1 shown in FIG. 10, the electrode pads 3 and the wires 6 to 8 are connected together via the bonding wires 11, having very fine dimensions, which are arranged in the through holes 10. This causes a problem in that a degree of freedom regarding wiring must be limited due to the through holes 10. When wiring is established within the same plane, the overall wiring length must be longer, which may cause another problem in that a wiring delay time is increased.
The very fine bonding wires 11 have a relatively large wiring resistance, which in turn increases a heating value thereof and imparts a bad influence to characterstics of the CSP 1.
In the WBCSP 21, the conduction pads 25 and the electrodes 23 are connected together via the bonding wires 26, whereby there is a problem in that short-circuit failure is likely to occur due to short-circuit of the bonding wires 26.
In addition, all of the conduction pads 25 and the electrodes 23 are connected using the bonding wires 26; hence, it is very difficult to reduce the overall distance between the conduction pads 25 and the electrodes. This may cause a difficulty in further reducing dimensions of the WBSCP 21.